A buck converter is a DC-to-DC power converter, which belongs to the class of Switched-Mode Power Supplies (SMPS). It is widely used throughout the industry to convert a higher input voltage into a lower output voltage. It is well-known in the art that this behavior may be achieved by alternatingly connecting an inductor according to a variable duty cycle (a) to the input terminal of the power converter using a high side switching element or (b) to ground using a low side switching element. In case the output voltage drops too fast below a pre-determined reference voltage, the power converter will attempt to maximize its duty cycle. This may happen during a load transient or when drawing too much current from the output of the power converter. In an synchronous valley mode current control architecture, for example, the maximum duty cycle may be limited by the minimum on-time of the low side switching element. This minimum on-time of the low side switching element severely depends on the delay of the continuous comparator used to compare an error voltage (indicating a difference between the actual output voltage and the reference voltage) and a ramp voltage.
Moreover, the maximum duty cycle of the power converter also sets the maximum speed at which the inductor current may be increased. It eventually also limits the maximum current that can be drawn from the output of the power converter if resistive losses are taken into account.
A similar limitation exists for the synchronous peak mode current control architecture. In this case, the minimum on-time of the high side switching element limits the minimum duty cycle of the power converter, and thereby limits the power converter's capability to decrease the inductor current, and eventually also to sink current at the output of the power converter.
To cope with these problems, the comparator delay has to be minimized. However, reducing the delay of a continuous comparator usually requires more bias current, and hence decreases the power efficiency of the converter. Therefore, delay minimization is only possible up to a certain extent. Another solution in conventional converters is to skip clock edges and thereby reduce the frequency of the output stage. This causes a higher current ripple, and also makes the frequency dependent on load conditions, which may not be desired in some applications.